Advanced Encryption Standard Circuit Research Articles

Profiling Deep Learning Side-Channel Attacks Using Multi-Label against AES Circuits with RSM Countermeasure

Deep learning side-channel attacks (DL-SCAs) have been actively studied in recent years. In the DL-SCAs, deep neural networks (DNNs) are trained to predict the internal states of the cryptographic operation from the side-channel information such as power traces. It is important to select suitable DNN output labels expressing an internal states for successful DL-SCAs. We focus on the multi-label method proposed by Zhang et al. for the hardware-implemented advanced encryption standard (AES). They used the power traces supplied from the AES-HD public dataset, and reported to reveal a single key byte on conditions in which the target key was the same as the key used for DNN training (profiling key). In this paper, we discuss an improvement for revealing all the 16 key bytes in practical conditions in which the target key is different from the profiling key. We prepare hardware-implemented AES without SCA countermeasures on ASIC for the experimental environment. First, our experimental results show that the DNN using multi-label does not learn side-channel leakage sufficiently from the power traces acquired with only one key. Second, we report that DNN using multi-label learns the most of side-channel leakage by using three kinds of profiling keys, and all the 16 target key bytes are successfully revealed even if the target key is different from the profiling keys. Finally, we applied the proposed method, DL-SCA using multi-label and three profiling keys against hardware-implemented AES with rotating S-boxes masking (RSM) countermeasures. The experimental result shows that all the 16 key bytes are successfully revealed by using only 2,000 attack traces. We also studied the reasons for the high performance of the proposed method against RSM countermeasures and found that the information from the weak bits is effectively exploited.

Electromagnetic Side-Channel Hardware Trojan Detection Based on Transfer Learning

Hardware Trojan detection method has been given particular attentions by hardware security researchers since the failure of Syrian radars in 2007. Electromagnetic side-channel analysis is a promising method which is widely used in practice due to its advantage of efficiency, non-touch and high accuracy. In this brief, we propose a novel method using electromagnetic side-channel signal for hardware Trojan detection by transfer learning. Firstly, time-frequency information of electromagnetic signal is extracted by continuous wavelet transform to take full advantage of useful information in time domain and frequency domain. Then, time-frequency information is fed to transfer learning network to get the classification result. In order to further improve the result, we use transfer learning to further extract the key features in time-frequency information. Finally, the key features are classified by the support vector machine to improve the accuracy. The experiment is conducted on a stand FPGA board and advanced encryption standard circuit is used as the benchmark circuit. Experimental results show that our methods can improve the result efficiently.

An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

AbstractA system‐on‐a‐chip (SoC) processor core contains several numbers of chips integrated into a single chip where each and every integrated circuit (IC) consists of multiple blocks. Hence, data routing from one chip to another creates a difficult issue in the SoC. A network‐on‐a‐chip (NoC) router has been mainly used to obtain highly reliable data transmission from a source to a destination using low power, low hardware complexity, and high speed to achieve efficient routing in the SoC core, which contains a router, network links (NLs), and network interface (NI). The heart of the NoC core, ie, the router, consists of a finite state machine (FSM), input/output FIFO, a crossbar switch, and an arbiter; however, the XY routing technique was incorporated into the NoC router to achieve high switching speed, and the FSM is used as a controller for the router along with the data stored in FIFO. The multiplexing and demultiplexing operations were also carried out in the crossbar switch in which a grant signal is being generated using the compact round‐robin arbiter and an Advanced Encryption Standard (AES) scheme, which is incorporated into the NoC router to achieve high reliability. The chief goal is to establish an efficient NoC router using an improved AES algorithm to achieve high reliability, small chip size, low power consumption, and high performance. Similarly, an optimized composite S‐box is designed using a compact multiplicative inverse unit with an improved inverse MixColumns structure proposed using compact 09, 0b, 0d, and 0e operations and retiming pipelined inclusively with clock gating methods (CGMs) applied in the targeted AES scheme. Hence, the retiming method can be used to shrink the number of registers by placing the register in an optimum location with low area and power in retiming‐based AES. The switching activity of the clock signal is reduced by using the CGM, which has low power consumption and high speed for clock gating–based AES. Therefore, the high performance–based AES is designed using a pipelined technique with high chip size and power due to the insertion of a large number of registers into the AES circuits. Five types of AES structures are designed, and the die size, delay, power, and 90% security with an optimized AES technique incorporated into a 3×3 NoC router with mesh topology are analyzed. Finally, the comparison between the existing and proposed NoC routers was carried out to analyze the area, delay, and power (ADP) product, and the NoC router design was formulated using Verilog HDL, and limitations along the synthesis process were executed using a ModelSim and Xilinx ISE tools.

Finding the key

Page 1114, ‘Deep learning (DL)-assisted and combined attack: a novel side-channel attack (SCA) ‘, W. Yu, J. Chen Researcher Weize Yu sitting adjacent to the cryptographic circuit setup testing the novel SCA technique. Flowchart illustrating the setup of the cryptographic system and paths to the secret key. Researchers from the Old Dominion University and the University of Minnesota Twin Cities in the US have exploited a deep learning (DL)-assisted and combined side-channel attack (SCA) method to disclose the secret key of an advanced encryption standard (AES) cryptographic circuit. The results demonstrate that, despite standard SCAs being ineffective even after 1 million plaintexts are enabled, the DL-assisted attack method requires only 32,500 plaintexts be enabled to leak the circuits secret key. Cryptographic circuits are the digital hardware implementations of cryptographic algorithms, used in situations which require private data to be processed confidentially and can be used for encrypting processors and Internet of Things (IoT) devices in our daily lives. Cryptographic algorithms are visible to the public while the secret (original) keys are private. Without obtaining the secret key, no one can unravel the relationship between the plaintexts and the ciphertexts for a cryptographic circuit. As a result, if the secret key of a cryptographic circuit is unknown, an adversary is incapable of leaking confidential information by exploring the correlation between the plaintexts (input data) and corresponding physical leakages such as EM noise. AES is the most popular cryptographic algorithm and, with the assistance of the original key, can encrypt plaintexts and decrypt ciphertexts. This encryption protects the data from external attacks, but AES is vulnerable to non-invasive malicious attacks such as SCAs. The teams Letter introduces a novel DL-assisted side-channel attack to obtain the secret key from an AES circuit and is the first work to test this approach. To secure AES cryptographic circuits, countermeasures like dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS) were proposed. These add random noises into physical leakage profiles to weaken the correlation between the processed data and the physical leakages to thwart standard SCAs. To break through this added layer of security, one of the authors Weize Yu notes that “the random noise inserted into different physical leakage profiles are strongly correlated and deep neural networks (DNN) can be utilised to model the correlation to filter the inserted random noises by combing two different physical leakages.” Ultimately, the protected AES cryptographic circuit can be cracked without much effort by a regular side-channel attack after filtering out the inserted random noises. If the DL technique is used to pre-process the physical leakages to enhance the correlation, the protected cryptographic circuit can be cracked easily with only 32,500 plaintexts being sufficient to leak the secret key. This work sets a representative example of combining side-channel analysis and machine learning to strengthen circuit attacks. Previously, side-channel attacks and machine learning attacks were two separate research areas. However, with the drastic development of machine learning, more algorithms have been demonstrated to be suitable for mining unknown information. By continuing to utilise machine learning to assist side-channel analysis, more secret information can be obtained more efficiently than with conventional techniques. The greatest challenge faced by the group was in designing a suitable DNN architecture that can model the relationship between the power noise and the EM emission noise efficiently and accurately. Since there was no solid theory to guide the teams design of the DNN, its features were determined empirically so as to find an appropriate DNN architecture to maximize the training efficiency. This required testing a variety of hidden layer and neuron numbers and analysing the sensitivities on the training error of the DNN, until the optimised results were acquired. The next step in the team's work, according to Yu, is “to demonstrate our novel attack on a cryptographic circuit which employs other countermeasures such as the masking technique.” This adds a random mask of data to the plaintext file generated by an embedded pseudo-random number generator (PRNG). The team will attempt to use the kernel support vector machine (SVM) algorithm to classify the output of the PRNG and the corresponding prediction accuracy achieves over 90%. This area is likely to achieve greater attention in the future given the recent focus on information security and privacy. More effort will be devoted to designing machine learning-resistant cryptographic circuits and these countermeasures may eventually win out. If both side-channel and machine learning attacks need to be considered, the design of more sophisticated cryptographic circuits is inevitable. As a result, designing cryptographic circuits against non-invasive attacks will be an area of key focus in future research.

Energy-efficient and security-optimized AES hardware design for ubiquitous computing

Ubiquitous computing must incorporate a certain level of security. For the severely resource con-strained applications, the energy-efficient and small size cryptography algorithm implementation is a critical prob-lem. Hardware implementations of the advanced encryption standard (AES) for authentication and encryption arepresented. An energy consumption variable is derived to evaluate low-power design strategies for battery-powered devices. It proves that compact AES architectures fail to optimize the AES hardware energy, whereas reducinginvalid switching activities and implementing power-optimized sub-modules are the reasonable methods. Implemen-tations of different substitution box (S-Boxes) structures are presented with 0.25 μm 1.8 V CMOS (complementarymetal oxide semiconductor) standard cell library. The comparisons and trade-offs among area, security, and powerare explored. The experimental results show that Galois field composite S-Boxes have smaller size and highestsecurity but consume considerably more power, whereas decoder-switch-encoder S-Boxes have the best power char-acteristics with disadvantages in terms of size and security. The combination of these two type S-Boxes instead ofhomogeneous S-Boxes in AES circuit will lead to optimal schemes. The technique of latch-dividing data path isanalyzed, and the quantitative simulation results demonstrate that this approach diminishes the glitches effectivelyat a very low hardware cost.

Dynamic inhomogeneous S-Boxes design for efficient AES masking mechanisms

It is an important challenge to implement a low- cost power analysis immune advanced encryption standard (AES) circuit. The previous study proves that substitution boxes (S-Boxes) in AES are prone to being attacked, and hard to mask for its non-linear characteristic. Besides, large amounts of circuit resources in chips and power consumption are spent in protecting S-Boxes against power analysis. Thus, a novel power analysis immune scheme is proposed, which divides the data-path of AES into two parts: inhomogeneous S-Boxes instead of fixed S-Boxes are selected randomly to disturb power and logic delay in the non-linear module; at the same time, the general masking strategy is applied in the linear part of AES. This improved AES circuit was synthesized with united microelectronics corporation (UMC) 0.25 μm 1.8 V complementary metal-oxide-semiconductor (CMOS) standard cell library, and correlation power analysis experiments were executed. The results demonstrate that this secure AES implementation has very low hardware cost and can enhance the AES security effectually against power analysis.